The present invention relates to a semiconductor package and a substrate thereof, and in particular to a semiconductor package and a substrate suitable for dense mounting, and a stacked semiconductor package which includes other semiconductor packages for stacking, which are stacked on the semiconductor package.
In resent years, a semiconductor device called CSP (Chip Size Package/Chip Scale Package) of BGA (Ball Grid Allay) type or QFP (Quad Flat Package) type, have been widely used for meeting a tendency to downsize electronic devices and automate its assembly process.
For high-speed signal processing and an improvement in the function of the semiconductor elements included in the foregoing semiconductor devices, a terminal for an electromagnetic shield and more terminals for input and output are required for the semiconductor package. Namely, more external terminals are now required in the foregoing semiconductor package.
For this reason, a package form called BGA type having external terminals disposed in a two-dimensional state on the bottom of the package has often been used because of its property which can provide more external terminals.
As an example of the BGA type semiconductor package, known is a semiconductor package in which a semiconductor chip is connected to the wiring substrate by a wire bonding with the circuit bearing side upward, and the electrodes of the semiconductor chip and the external terminals are conductive each other via a wiring pattern arranged on the wiring substrate.
The following will explain a semiconductor package as a resin sealing type semiconductor device using the foregoing conventional technique with reference to FIG. 9. Firstly, through holes 37 are formed in an insulating substrate 31 in accordance with the alignment pattern of external terminals of the BGA type. Then, terminal sections 33 for connecting to a semiconductor chip 44 (described later) are formed on the periphery of the insulating substrate 31.
Further, to prepare a wiring substrate 32, wiring patterns 43 are provided on the insulating substrate 31 by a Cu foil so that each end is exposed via the through holes 37. Next, the semiconductor chip 44 is mounted on the wiring substrate 32, and the semiconductor chip 44 and the terminal sections 33 are connected to each other by Au wires 34.
A sealing resin section 35 for sealing the semiconductor chip 44, the terminal sections 33, and the Au wires 34 is formed by a transfer mold method. Solder balls 36 are provided as connecting external terminals by a reflow connection so as to be connected to the wiring patterns 43 via the through holes 37.
Further, among these, a semiconductor package such as a memory mounted on a portable device is required to be downsized, and also required to increase the memory amount and the processing amount for adding a greater value. In order to meet these requirements, the semiconductor package having a plurality of semiconductor chips in a single package has been known.
As an example of this type of semiconductor package, a multi-chip module having a plurality of horizontally aligned semiconductor chips has been known; however, in this type of package, since the semiconductor chips are horizontally aligned, the semiconductor package will not be smaller than the gross area of the mounted semiconductor chips.
Meanwhile, known is a semiconductor package having a plurality of semiconductor chips stacked in a single package (hereinafter, referred to as a stacked package) so as to increase packaging density.
As an example of the stacked packages, Japanese Unexamined Patent Publication No. 204720/1999 (Tokukaihei 11-204720 published on Jul. 30, 1999, corresponding to the U.S. Pat. No. 6,100,594 granted on Aug. 8, 2000) discloses a semiconductor package having the CSP structure of substantially the chip size in which the semiconductor chip is mounted on an electrically insulative substrate, and the connecting external terminals are provided in a matrix manner on the rear surface of the electrically insulative substrate.
FIG. 10 schematically shows an arrangement of a stacked package having the foregoing structure. This stacked package is formed by die-bonding a first semiconductor chip 44a on the wiring substrate 32 with the circuit bearing side upward and die-bonding a second semiconductor chip 44b thereon. Thereafter, the first and second semiconductor chips 44a and 44b, and each terminal section 33 of the wiring substrate 32 are connected to each other using the Au wires 34 by a wire bonding method.
Further, a sealing resin section 35 is formed so as to seal the first and second semiconductor chips 44a and 44b, the terminal sections 33, and the Au wires 34, by the transfer mold method. Then, the solder balls 36 are formed as the external connecting terminals by the reflow connection so as to be connected to the wiring pattern 43 via the through holes 37.
This type of stacking can be performed when stacking semiconductor chips of three or so; however, when more semiconductor chips are stacked, stacking these semiconductor packages instead of stacking the semiconductor chips is more advantageous in terms of the yield. As an example of a semiconductor package for the stacking, a stacking semiconductor package 52 shown in FIG. 11 in which external terminals 54 are provided outside of the mounting area of the semiconductor chip 44 has been known.
The stacking semiconductor package 52 has an opening section 52a in the center of an insulating substrate 31, which is sized to be the mounting area of the semiconductor chip 44, and the package 52 includes the external terminals 54 in the peripheries of both surfaces of the insulating substrate 31. Also, the solder balls are provided on the external terminals 54 of one surface (normally, the rear surface) of the insulating substrate 31.
Then, as shown in FIG. 12, a plurality of the stacking semiconductor package 52 are stacked in the thickness direction, and the solder balls 36 are connected to the corresponding external terminals so as to be completed as the stacked semiconductor package.
In the stacked semiconductor package thus described, the connecting external terminals 54 are required to be respectively provided on the front surface and the rear surface so as to ensure electrical continuity between the vertically adjacent semiconductor packages 52, in other words, the semiconductor packages 52 adjacent in the thickness direction.
Therefore, in the stacking semiconductor package 52 having the structure of FIG. 11, the external terminals 54 are provided outside of the mounting area of the semiconductor chip 44 on the insulating substrate 31 to be joined to each other.
Incidentally, in the stacking semiconductor package 52 having the foregoing structure, it is necessary to increase packaging efficiency and density of semiconductor chips with respect to the mounting area of the semiconductor package. Therefore, the stacking semiconductor package 52 is required to be downsized.
Accordingly, the area of the external terminals 54 is required to be set as small as possible, which are provided outside of the mounting area of the semiconductor chip 44. Thus, a pitch between the external terminals 54 is required to be set as small as possible.
In the foregoing stacked semiconductor package having a plurality of the semiconductor packages 52 stacked thereon, the stacking of the semiconductor packages 52 is possibly performed by a package manufacturer; however, the mounting of the semiconductor package 52 on the bottom of the stack to a mounting substrate, in other words, to a motherboard, is often performed by a user.
However, in the foregoing conventional stacked semiconductor package, it has been difficult to stably mount the stacking semiconductor package 52 to the motherboard while keeping a large number of the external terminals 54, and the yield of the stacked semiconductor package adopting the stacking semiconductor packages 52 has been decreased due to such as a poor connection.
Namely, as described, there is a limitation for a stable mounting of the semiconductor package 52 to a motherboard by a user, when the semiconductor package 52 has a pitch, which is set as small as possible, between the external terminals 54. Accordingly, with the foregoing conventional stacked semiconductor package, it has been difficult to stably connect and mount the stacking semiconductor package 52, which has the external terminal 54 with the small pitch, to the motherboard while keeping a large number of the external terminals 54, and the yield of the stacked semiconductor package having the semiconductor packages 52 stacked in the thickness direction, has been decreased.
In order to solve the afore-stated problems, the semiconductor package substrate of the present invention includes:
a first wiring substrate 1, which has a first metal pattern for external connection of a semiconductor chip, and is provided on a first surface, including first wire bonding terminal sections, wiring sections, and first connecting terminal land sections, and an opening section for mounting a semiconductor chip;
a second wiring substrate, which has a second metal pattern including second wire bonding terminal sections and second connecting terminal land sections on a first surface, and through holes so that the second connecting terminal land sections on the first surface communicate to the second surface which is opposite to the first surface, the second surface of the first wiring substrate and the first surface of the second wiring substrate being combined so that the second wire bonding terminal sections are exposed.
With the foregoing arrangement, since the first wiring substrate has the opening section, the semiconductor chip can be mounted to the opening section, and electrical continuity with respect to the semiconductor chip is ensured via the first wire bonding terminal sections.
Further, in the foregoing arrangement, since the first wiring substrate has the wiring sections and the first connecting terminal land sections, electrical continuity between the first wire bonding terminal sections and the first connecting terminal land sections is ensured via the wiring sections, and it becomes possible to stack other semiconductor packages thereon, and electrical connection between the first wiring substrate and the stacked semiconductor packages can be ensured via the first connecting terminal land sections which are formed on the first surface of the first wiring substrate except for the mounting area of the semiconductor chip, i.e., the opening section.
Further, since the second wire bonding terminal sections of the second wiring substrate are exposed, it is possible to electrically connect the second wire bonding terminal sections to the semiconductor chip or the first wire bonding terminal sections. Further, the through holes are provided on the second wiring substrate so that the second connecting terminal land sections on the first surface of the second wiring substrate communicate to the second surface which is opposite to the first surface, thereby electrically connecting the second connecting terminal land sections to the second surface.
As described, in the foregoing arrangement, it is possible to dispose the second connecting terminal land sections on the second wiring substrate regardless of the mounting area of the semiconductor chip. Therefore, a large number of the second connecting terminal land sections, which are external terminals to, for example, the mounting substrate, communicating to the second surface, can be provided. Also, the pitch between the second connecting terminal land sections can be set to a greater interval.
Consequently, the yield will not decrease in the stacked semiconductor package having the foregoing arrangement.
In order to solve the afore-stated problems, the semiconductor package of the present invention includes:
a first wiring substrate, which has a first metal pattern for external connection of a semiconductor chip, and is provided on a first surface including first wire bonding terminal sections, wiring sections, first connecting terminal land sections, and an opening section for mounting a semiconductor chip;
a second wiring substrate, which has a second metal pattern including second wire bonding terminal sections and second connecting terminal land sections on a first surface, and through holes so that the second connecting terminal land sections on the first surface communicate to the second surface which is opposite to the first surface;
a semiconductor package substrate made up by mating the second surface of the first wiring substrate and the first surface of the second wiring substrate in the state where the second wire bonding terminal sections are exposed;
a semiconductor chip mounted on the metal pattern of the second wiring substrate via the opening with a circuit bearing side facing opposite to the second wiring substrate;
metal wires for causing electrical continuity among electrode pads of the semiconductor chip, the first wire bonding terminal sections, and the second wire bonding terminal sections;
a resin sealing section which covers and seals the semiconductor chip, the first wire bonding terminal sections, and the second wire bonding terminal sections; and
external terminals formed on the second connecting terminal land sections.
In the foregoing arrangement, it is possible to dispose the second connecting terminal land sections on the second wiring substrate regardless of the mounting area of the semiconductor chip. Therefore, a large number of the second connecting terminal land sections which are external terminals to, for example, the mounting substrate, communicating to the second surface, can be provided, and the pitch between the second connecting terminal land sections can be set to a greater interval. Consequently, the yield will not decrease in the stacked semiconductor package having the foregoing arrangement.
Additional objects, features, and strengths of the present invention will be made clear by the description below. Further, the advantages of the present invention will be evident from the following explanation in reference to the drawings.